View ADVANCEDPOWERELECTRONICSCORP-APU3048O_7002104.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

apu3048 1 data and specifications subject to change without notice. typical application description the apu3048 ic combines a dual synchronous buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. the dual synchronous con- troller is configured as 2-independent pwm controller. apu3048 provides a separate adjustable output by driv- ing a switch as a linear regulator. this device features an internal 200khz oscillator, under-voltage lockout for all input supplies, an external programmable soft start func- tion as well as output under-voltage detection that latches off the device when an output short is detected. dual synchronous controller in 16-pin package with 180 8 out-of-phase operation ldo controller with 40ma drive configured as 2-independent pwm controller flexible, same or separate supply operation operation from 4v to 25v input internal 200khz oscillator soft-start controls all outputs fixed frequency voltage mode 500ma peak output drive capability programmable outputs rohs compliant package order information features dual synchronous pwm controller circuitry and ldo controller applications ta (c) device package 0 to 70 apu3048o 16-pin tssop 0 to 70 apu3048m 16-pin soic nb preliminary data sheet technology licensed from international rectifier figure 1 - typical application of apu3048 configured as 2-independent converter. ddr memory source sink vtt application graphic card hard disk drive power supplies requiring multiple outputs 12v 5v v out3 c1 r2 q5 l2 q4 q1 c2 3.3v u1 vout1 r6 l1 r5 c5 r1 r4 c4 r3 c3 pgnd vout3 ldrv1 hdrv1 fb1 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss apu3048 q3 q2 vout2 c6 r7 c7 r8 r2 1n4148 1n4148 200806093
2 apu3048 electrical specifications unless otherwise specified, these specifications apply over vcc=5v, vch1=vch2=12v, t a =0 to 70c. typical values refer to t a =25c. low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. absolute maximum ratings vcc supply voltage .................................................. 25v vch1=vch2 supply voltage ...................................... 30v (not rated for inductive load) storage temperature range ...................................... -65c to 150c operating junction temperature range ..................... 0c to 125c package information 16-pin plastic tssop (o) 16-pin plastic soic nb (m) parameter sym test condition min typ max units reference voltage fb voltage fb voltage line regulation uvlo uvlo threshold - vcc uvlo hysteresis - vcc uvlo threshold - vch1 uvlo hysteresis - vch1 uvlo threshold - vch2 uvlo hysteresis - vch2 uvlo threshold - fb uvlo hysteresis - fb supply current vcc dynamic supply current vch1 dynamic supply current vch2 dynamic supply current vcc static supply current vch1 static supply current vch2 static supply current soft-start section charge current 5 apu3048 3 parameter sym test condition min typ max units pin descriptions pin# pin symbol pin description error amp fb voltage input bias current fb voltage input bias current transconductance 1 transconductance 2 oscillator frequency ramp amplitude output drivers rise time fall time dead band time max duty cycle min duty cycle ldo controller drive current fb voltage input bias current ss=3v ss=0v c l =1500pf c l =1500pf fb=1v, freq=200khz fb=1.5v 180 50 85 0 30 1.225 -0.1 -64 400 600 200 1.25 35 50 150 90 0 45 1.25 0.5 220 100 100 250 1.275 2 m a m a m mho m mho khz v pp ns ns ns % % ma v m a 1 2 16 3 4 5 12 6 11 7 10 8 9 13 14 15 gnd fb2 fb1 comp1 comp2 vch2 vch1 hdrv2 hdrv1 ldrv2 ldrv1 pgnd vcc v out3 fb3 ss ground pin. inverting inputs to the error amplifiers. these pins work as feedback inputs for each channel, and are connected directly to the output of the switching regulator via a resistor divider to set the output voltages. compensation pins for the error amplifiers. supply voltage for the high side output drivers. these are connected to voltages that must be at least 4v higher than their bus voltages (assuming 5v threshold mosfet). a minimum of 1 m f high frequency capacitor must be connected from these pins to pgnd pin to provide peak drive current capability. output driver for the high side power mosfet. connect a diode, such as bat54 or 1n4148, from these pins to ground for the application when the inductor current goes negative (source/sink), soft-start at no load and for the fast load transient from full load to no load. output driver for the synchronous power mosfet . this pin serves as the separate ground for mosfet?s driver and should be connected to the system?s ground plane. supply voltage for the internal blocks of the ic. driver signal for the ldo?s external transistor. ldo?s feedback pin, connected to a resistor divider to set the output voltage of ldo. soft-start pin. the converter can be shutdown by pulling this pin below 0.5v. i fb1 i fb2 g m1 g m2 freq v ramp tr tf t db t on t off i ldo v fb ldo i ldo(bias)
4 apu3048 block diagram figure 2 - block diagram of the apu3048. bias generator ldrv2 two phase oscillator 1.25v 3v ramp1 fb3 0.5v por por gnd hdrv2 vch2 ss comp2 error amp2 pwm comp2 por v out3 25ua reset dom ldrv1 hdrv1 vch1 fb1 comp1 error amp1 pwm comp1 25k 25k reset dom set1 set2 ramp2 64ua max uvlo vch2 3.5v / 3.3v vch1 3.5v / 3.3v 4.2v / 4.0v fb2 25k 40ma ldo controller pgnd vcc 1.25v 1.25v ss > 2v r s q s r q vcc 9 15 16 3 2 4 14 1 12 11 10 5 6 7 8 13 1.25v 2v ss 25k 25k 25k
apu3048 5 theory of operation introduction the apu3048 is designed for multi-outputs applications. it includes two synchronous buck controllers and a lin- ear regulator controller. the two synchronous controller operates with fixed frequency voltage mode and is con- figured as two independent controllers. the timing of the ic is provided through an internal oscillator circuit. these are two out of phase oscillators. soft-start the apu3048 has a programmable soft start to control the output voltage rise and limit the current surge at the start-up. to ensure correct start-up, the soft-start se- quence initiates when the vcc, vch1 and vch2 rise above their threshold and generates the power on re- set (por) signal. soft-start function operates by sourc- ing an internal current to charge an external capacitor to about 3v. initially, the soft-start function clamps the e/ a?s output of the pwm converter. as the charging volt- age of the external capacitor ramps up, the pwm sig- nals increase from zero to the point the feedback loop takes control. out of phase operation the apu3048 drives its two output stages 1808 out of phase. in application with single input voltage, the out of phase operation reduces the input ripple current. this results in much smaller rms current in the input ca- pacitor and reduction of input capacitors. shutdown the converter can be shutdown by pulling the soft-start pin below 0.5v. this can be easily done by using an external small signal transistor. during shutdown the mosfet drivers and the ldo controller turn off. short-circuit protection the outputs are protected against the short circuit. the apu3048 protects the circuit for shorted output by sens- ing the output voltages. the apu3048 shuts down the pwm signals and ldo controller, when the output volt- ages drops below the set values. under-voltage lockout the under-voltage lockout circuit assures that the mosfet driver outputs and ldo controller remain in the off state whenever the supply voltages drop below set parameters. normal operation resumes once the supply voltages rise above the set values. application information design example: the following example is a typical application for apu3048 in current sharing mode. the schematic is figure 9 on page 12. pwm section output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb1 pin is the inverting input of the error amplifier, which is internally referenced to 1.25v. the divider is ratioed to provide 1.25v at the fb1 pin when the output is at its desired value. the output voltage is defined by using the following equation: fb1 apu3048 v out1 r 8 r 6 when an external resistor divider is connected to the output as shown in figure 3. figure 3 - typical application of the apu3048 for programming the output voltage. equation (1) can be rewritten as: v out1 = v ref 3 1+ ---(1) ( ) r 6 r 8 will result to: v out1 =3.3v v ref =1.25v r 8 =1k, r 6 =1.64k v out2 =1.8v v ref =1.25v r 15 =1k, r 14 =442 v r 6 = r 8 3 - 1 v out1 v ref ( ) for switcher v in1 = 12v v out1 = 3.3v i out1 = 4a v in2 = 5v v out2 = 1.8v i out2 = 4a d v out = 75mv f s = 200khz for linear regulator v in3 = 3.3v v out3 = 2.5v i out3 = 2a
6 apu3048 output capacitor selection the criteria to select the output capacitor is normally based on the value of the effective series resistance (esr). in general, the output capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy sta- bility requirements. the esr of the output capacitor is calculated by the following relationship: the sanyo tpc series, poscap capacitor is a good choice. the 6tpc150m 150 m f, 6.3v has an esr 40m v . selecting two of these capacitors in parallel for each output, results to an esr of @ 20m v which achieves our low esr goal. the capacitor value must be high enough to absorb the inductor's ripple current. the larger the value of capaci- tor, the lower will be the output ripple voltage. the resulting output ripple current is smaller then each channel ripple current due to the 180 8 phase shift. these currents cancel each other. the cancellation is not the maximum because of the different duty cycle for each channel. inductor selection the inductor is selected based on output power, operat- ing frequency and efficiency requirements. low induc- tor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( d i); the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: if the high value feedback resistors are used, the input bias current of the fb pin could cause a slight increase in output voltage. the output voltage set point can be more accurate by using precision resistor. soft-start programming the soft-start timing can be programmed by selecting the soft start capacitance value. the start up time of the converter can be calculated by using: where: c ss is the soft-start capacitor ( m f) for a start-up time of 7.5ms, the soft-start capacitor will be 0.1 m f. choose a ceramic capacitor at 0.1 m f. boost supply vc to drive the high-side switch it is necessary to supply a gate voltage at least 4v greater than the bus voltage. this is achieved by using a charge pump configuration as shown in figure 9. the capacitor is charged up to approximately twice the bus voltage. a capacitor in the range of 0.1 m f to 1 m f is generally adequate for most applications. input capacitor selection the input filter capacitor should be based on how much ripple the supply can tolerate on the dc input line. the ripple current generated during the on time of control mosfet should be provided by input capacitor. the rms value of this ripple is expressed by: where: d is the duty cycle, simply d=v out /v in. i rms is the rms value of the input capacitor current. i out is the output current for each channel. for v in1 =12v, i out1 =4a and d1=0.275 results to: i rms1 =1.78a and for v in2 =5v, i out2 =4a and d2=0.36 results to: i rms2 =1.92a for higher efficiency, a low esr capacitor is recom- mended. for v in1 =12v, choose one poscap from sanyo 16tpb47m (16v, 47 m f, 70m v , 1.4a) for v in2 =5v, choose one 6tpc150m (6.3v, 150 m f, 40m v , 1.9a). t start = 75 3 css (ms) ---(2) i rms = i out d 3 (1-d) ---(3) esr [ ---(4) d v o d i o where: d v o = output voltage ripple d i o = output current d v o =75mv and d i o =3a, results to: esr=25m v v in - v out = l 3 ; d t = d 3 ; d = 1 f s v out v in d i d t l = (v in - v out ) 3 ---(5) v out v in 3d i 3 f s where: v in = max input voltage v out = output voltage d i = inductor ripple current f s = switching frequency d t = turn on time d = duty cycle
apu3048 7 for d i 1 =25% of i 1 , we get l 1 =9.9 m h for d i 2 =25% of i 2 , we get: l 2 =5.7 m h panasonic provides a range of inductors in different val- ues and low profile for large currents. for l 1 choose etqp6f102hfa (10.2 m h, 4a) for l 2 choose ellatv6r8m (6.8 m h, 4a) power mosfet selection the selections criteria to meet power transfer require- ments is based on maximum drain-source voltage (v dss ), gate-source drive voltage (v gs ), maximum output cur- rent, on-resistance r ds(on) and thermal management. the mosfet must have a maximum operating voltage (v dss ) exceeding the maximum input voltage (v in ). the gate drive requirement is almost the same for both mosfets. caution should be taken with devices at very low v gs to prevent undesired turn-on of the complemen- tary mosfet, which results a shoot-through current. the total power dissipation for mosfets includes con- duction and switching losses. for the buck converter the average inductor current is equal to the dc load cur- rent. the conduction loss is defined as: the total conduction loss is defined as: the r ds(on) temperature dependency should be consid- ered for the worst case operation. this is typically given in the mosfet data sheet. ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. for this design, ap9408agh is a good choice. these devices provide low on-resistance in a compact to-252 3pin package. the mosfets have the following data: the total conduction losses for channel 1 is: the total conduction losses for channel 2 is: the control mosfet contributes to the majority of the switching losses in synchronous buck converter. the synchronous mosfet turns on under zero-voltage con- dition, therefore the turn on losses for synchronous mosfet can be neglected. with a linear approxima- tion, the total switching loss can be expressed as: figure 4 - switching time waveforms. from ap9408agh data sheet we obtain: these values are taken under a certain condition test. for more detail please refer to the ap9408agh data sheet. by using equation (6), we can calculate the switching losses. p con1 = 0.24w p con2 = 0.24w ap9408agh v dss = 30v i d = 3 3 a @ 1008c r ds(on) = 10m v @ v gs =10v q = 1.5 for 150 8 c (junction temperature) where: v ds(off) = drain to source voltage at off time t r = rise time t f = fall time t = switching period i load = load current p sw = 3 3 i load ---(6) v ds(off) 2 t r + t f t 2 2 p cond (upper switch) = i load 3 r ds(on) 3 d 3q p cond (lower switch) = i load 3 r ds(on) 3 (1 - d) 3q q = r ds(on) temperature dependency p con(total) =p con (upper switch) q +p con (lower switch) q ap9408agh t r = 5ns t f = 6ns p sw1 = 52.8mw p sw2 = 22mw v ds v gs 10% 90% t d (on) t d (off) t r t f
8 apu3048 feedback compensation the apu3048 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensa- tion circuit is necessary. the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency and adequate phase margin (greater than 45 8 ). the output lc filter introduces a double pole, ?40db/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 8 (see figure 5). the reso- nant frequency of the lc filter is expressed as follows: figure 5 shows gain and phase of the lc filter. since we already have 180 8 phase shift just from the output filter, the system risks being unstable. figure 5 - gain and phase of lc filter. the apu3048's error amplifier is a differential-input transconductance amplifier. the output is available for dc gain control or ac phase compensation. the e/a can be compensated with or without the use of local feedback. when operated without local feedback the transconductance properties of the e/a become evi- dent and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp1 pin to ground as shown in figure 6. the esr zero of the lc filter expressed as follows: figure 6 - compensation network without local feedback and its asymptotic gain plot. the transfer function (ve / v out ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: the gain is determined by the voltage divider and e/a's transconductance gain. first select the desired zero-crossover frequency (fo): use the following equation to calculate r4: f o1 > f esr and f o1 [ (1/5 ~ 1/10) 3 f s v out v ref r 8 r 6 r 9 c 18 ve e/a f z h(s) db frequency gain(db) fb comp f lc = ---(7) 1 2 p lo 3 co f esr = ---(8) 1 2 p 3 esr 3 co h(s) = g m 3 3 ---(9) r 8 r 6 + r 8 1 + sr 9 c 18 sc 18 ( ) |h(s)| = g m 3 3 r 9 ---(10) f z = ---(11) 1 2 p 3 r 9 3 c 18 r 8 r 6 3 r 8 r 9 = ---(12) v osc v in1 f o1 3 f esr1 f lc1 2 r 8 + r 6 r 8 1 g m 3 3 3 where: v in1 = maximum input voltage v osc = oscillator ramp voltage f o1 = crossover frequency for the master e/a f esr1 = zero frequency of the output capacitor f lc1 = resonant frequency of output filter g m = error amplifier transconductance r 8 and r 6 = resistor dividers for output voltage programming gain f lc 0db phase 0 8 f lc -180 8 frequency frequency -40db/decade
apu3048 9 this results to r 9 =46.4k v ; choose r 9 =46.4k v to cancel one of the lc filter poles, place the zero be- fore the lc filter resonant frequency pole: using equations (11) and (13) to calculate c 9 , we get: using equations (11),(12) and (13) for ch2, where: we get: r 11 = 38.9k v ; choose r 11 = 39.2k v c 19 = 1554pf; choose c 19 = 1800pf one more capacitor is sometimes added in parallel with c 9 and r 4 . this introduces one more pole which is mainly used to supress the switching noise. the additional pole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole: for a general solution for unconditionally stability for any type of output capacitors, in a wide range of esr values we should implement local feedback with a compensa- tion network. the typically used compensation network for voltage-mode controller is shown in figure 7. c 9 = 1630pf; choose c 9 = 1800pf v in2 = 5v v osc = 1.25v f o2 = 30khz f esr2 = 26.5khz f lc2 = 3.5khz r 15 = 1k r 14 = 442 v g m = 600 m hmo f z @ 75%f lc1 f z @ 0.75 3 1 2 p l 3 3 c o ---(13) for: l 3 = 10.2 m h co = 300 m f fz = 2.1khz r 9 = 46.4k v figure 7 - compensation network with local feedback and its asymptotic gain plot. in such configuration, the transfer function is given by: the error amplifier gain is independent of the transcon- ductance under the following condition: by replacing z in and z f according to figure 7, the trans- former function can be expressed as: as known, transconductance amplifier has high imped- ance (current source) output, therefore, consider should be taken when loading the e/a output. it may exceed its source/sink output current capability, so that the ampli- fier will not be able to swing its output voltage over the necessary range. the compensation network has three poles and two ze- ros and they are expressed as follows: v e 1 - g m z f 1 + g m z in v out = c pole = @ p 3 r 9 3 f s - 1 c 18 1 1 p 3 r 9 3 f s for f p << f s 2 f p = 2 p 3 r 9 3 c 18 3 c pole c 18 + c pole 1 v out v ref r 5 r 6 r 8 c 10 c 12 c 11 r 7 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp g m z f >> 1 and g m z in >>1 ---(14) for: v in1 = 12v v osc = 1.25v f o1 = 30khz f esr1 = 26.5khz f lc1 = 2.8khz r 8 = 1k r 6 = 1.64k g m = 600 m mho h(s)= sr 6 (c 12 +c 11 ) 1+sr 7 3 (1+sr 8 c 10 ) 1 (1+sr 7 c 11 ) 3 [1+sc 10 (r 6 +r 8 )] 3 c 12 c 11 c 12 +c 11 [ ( )] f p1 = 0 1 2 p3 c 10 3 (r 6 + r 8 ) f z2 = @ 1 2 p3 c 10 3 r 6 f z1 = 1 2 p3 r 7 3 c 11 f p3 = @ 1 2 p3 r 7 3 f p2 = 1 2 p3 r 8 3 c 10 1 2 p3 r 7 3 c 12 c 12 3 c 11 c 12 +c 11 ( )
10 apu3048 cross over frequency: the stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. the consideration has been taken to satisfy condition 14 regarding transconduc- tance error amplifier. 1) select the crossover frequency: 2) select r 7 , so that r 7 >> 3) place first zero before lc?s resonant frequency pole. 4) place third pole at the half of the switching frequency. c 12 > 50pf if not, change r 7 selection. 5) place r 7 in (15) and calculate c 10 : 6) place second pole at esr zero. f p2 = f esr check if r 8 > if r 8 is too small, increase r 7 and start from step 2. 7) place second zero around the resonant frequency. f z2 = f lc f p3 = f s 2 8) use equation (1) to calculate r 5 : these design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. the higher the band width, the potentially faster the load tran- sient speed. the gain margin will be large enough to provide high dc-regulation accuracy (typically -5db to - 12db). the phase margin should be greater than 45 8 for overall stability. ldo section output voltage programming output voltage for ldo is programmed by reference volt- age and external voltage divider. the fb3 pin is the in- verting input of the error amplifier, which is internally ref- erenced to 1.25v. the divider is ratioed to provide 1.25v at the fb3 pin when the output is at its desired value. the output voltage is defined by using the following equa- tion: results to: r high =1k ldo power mosfet selection the first step in selecting the power mosfet for the linear regulator is to select the maximum r ds(on) based on the input to the dropout voltage and the maximum load current. results to: r ds(on)(max) = 0.4 v note that since the mosfet r ds(on) increases with tem- perature, this number must be divided by ~1.5 in order to find the r ds(on)(max) at room temperature. the ap20t03gh has a maximum of 0.05v rds(on) at room temperature, which meets our requirements. 1 g m c 12 = 1 2 p 3 r 7 3 f p3 c 10 [ 3 2 p 3 lo 3 f o 3 co r 7 v osc v in r 8 = 1 2 p 3 c10 3 f p2 r 6 = - r 8 1 2 p 3 c10 3 f z2 r 5 = 3 r 6 v ref v out - v ref r ds(on) = v in3 - v out2 i out2 for: v in3 = 3.3v v out2 = 2.5v i out2 = 2a where: v in = maximum input voltage v osc = oscillator ramp voltage lo = output inductor co = total output capacitors f o1 = r 7 3 c 10 3 3 v in v osc 1 2 p3 lo 3 co ---(15) fo < f esr and fo [ (1/10 ~ 1/6) 3 f s 2 g m f z1 @ 75% f lc c 11 = 1 2 p 3 f z1 3 r 7 for: v out2 = 2.5v v ref = 1.25v r low = 1k ( ) r high r low v out2 = v ref 3 1+
apu3048 11 layout consideration the layout is very important when designing high fre- quency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start to place the power components, make all the con- nection in the top layer with wide, copper filled areas. the inductor, output capacitor and the mosfet should be close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place input capacitor directly to the drain of the high-side mosfet, to reduce the esr replace the single input capacitor with two par- allel units. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. in multilayer pcb use one layer as power ground plane and have a control cir- cuit ground (analog ground), to which all signals are ref- erenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. typical application 12v to 3.3v @ 4a 12v to 1.8v @ 4a 3.3v to 2.5v @ 2a figure 8 - typical application of apu3048 in an on-board dc-dc converter using a single 12v supply for switcher. 12v 2.5v @ 2a c9 47uf r7 1k ap9412agh l4 ap9408agh c8 1uf c15 47uf 3.3v u1 3.3v @ 4a r8 1k c13 1uf l3 c16 47uf r6 1.65k c24 0.1uf r5 r11 c19 r9 c18 c1 1uf pgnd v out3 ldrv1 hdrv1 fb1 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss apu3048 ap9412agh ap9408agh c6 47uf c3 0.1uf 10uh 6.8uh 1.8v @ 4a r15 1k r14 442 v fb2 1k q1 ap20t03gh l1 1uh c2 33uf d1 bat54s c14 1uf r2 10 v c7 1uf c17 1uf c10 470pf r4 4.7 v c20 470pf r13 4.7 v c11, c12 2x 150uf 1800pf 3900pf 43.2k 16.2k c21, c22 2x 150uf c23 1uf 1n4148 1n4148 q3 q3 q2 q2
12 apu3048 demo-board application 12v to 3.3v @ 4a 5v to 1.8v @ 4a 3.3v to 2.5v @ 2a figure 9 - demo-board application of apu3048. 12v 5v 2.5v @ 2a c4 33uf l1 c9 47uf r7 1k ap9412agh l3 ap9408agh c8 1uf c15 47uf 3.3v u1 3.3v @ 4a r8 1k c13 1uf l4 c16 150uf r6 1.65k c24 0.1uf r5 r11 c19 r9 c18 c5 1uf c1 1uf pgnd v out3 ldrv1 hdrv1 fb1 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss apu3048 ap9412agh ap9408agh c6 47uf 1uh c3 0.1uf 10.2uh 6.8uh 1.8v @ 4a r15 1k r14 442 v fb2 1k q1 ap20t03gh l2 1uh c2 33uf d1 bat54s c14 1uf r2 10 v c7 1uf c17 1uf c10 470pf r4 4.7 v c20 470pf r13 4.7 v c11, c12 2x 150uf 1800pf 1800pf 46.4k 39.2k c21, c22 2x 150uf c23 1uf r1 r3 r10 r12 2.15 v 2.15 v 2.15 v 2.15 v 1n4148 1n4148 q2 q2 q3 q3
apu3048 13 ref desig description value qty part# manuf web site (www.) 1 2 1 1 2 1 1 7 2 2 1 2 2 2 1 5 4 1 2 4 1 1 1 1 q1 q2 u1 d1 l1, l2 l3 l4 c1,7,8,13, 14,17,23 c2, c4 c3, c24 c5 c9, c15 c10, c20 c18, c19 c6 c11,12,16 21,22 r1,3,10,12 r2 r4, r13 r5,7,8,15 r6 r9 r11 r14 mosfet mosfet controller diode inductor inductor inductor cap, ceramic cap, tantalum cap, ceramic cap, ceramic cap, tantalum cap, ceramic cap, ceramic cap, poscap cap, poscap resistor resistor resistor resistor resistor resistor resistor resistor ap20t03gh ap9408agh apu3048 bat54s ell6sh1r0m ellatv6r8m etqp6f102hfa ecj-2vf1c105z ecs-t1cd336r ecj-2vf1e104z ecj-3yb1e105k ecs-t1ad476r ecj-2vc1h471j ecj-2vb1h182k 16tpb47m 6tpc150m apec apec apec ir panasonic panasonic panasonic panasonic panasonic panasonic panasonic panasonic panasonic panasonic sanyo sanyo 30v, 50mohm, 1.5a 30v, 10m ohm, 53a synchronous pwm fast switching 1mh, 2.9a 6.8mh, 4a 10.2mh, 4a 1mf, y5v, 16v 33mf, 16v 0.1mf, y5v, 25v 1mf, x7r, 25v 47mf, 10v 470pf, x7r, 50v 1800pf, x7r, 50v 47mf, 16v, 70mv 150mf, 6.3v, 40mv 2.15v 10v 4.7v 1k, 1% 1.65k, 1% 46.4k 39.2k 442v, 1% a-power.com.tw maco.panasonic.co.jp sanyo.com/industrial demo-board application 12v to 3.3v @ 4a 5v to 1.8v @ 4a 3.3v to 2.5v @ 2a q3 mosfet 30v, 6mohm, 68a 2 ap9412agh apec
14 apu3048 figure 7 - output voltage ripple for 3.3v @ 4a. figure 4 - transient response @ i out = 0 to 2a for 3.3v output. waveforms figure 5 - transient response @ i out = 0 to 2a for 1.8v output. figure 6 - transient response @ i out = 0 to 2a for 2.5v output. 2a 0a 2a 0a
apu3048 15 figure 9 - gate signals for 3.3v output. ch1: output current 2a/div. ch2: gate signal for control fet 20v/div. ch3: gate signal for sync fet 10v/div. figure 11 - gate signals for 1.8v output. ch1: output current 2a/div. ch2: gate signal for control fet 10v/div. ch3: gate signal for sync fet 10v/div. waveforms figure 8 - output voltage ripple for 1.8v @ 4a. figure 10 - soft-start voltage vs. output voltages. v out1 : 3.3v v out2 : 1.8v v out3 : 2.5v vss
package outline : sop-16 millimeters min nom max a 1.47 1.60 1.73 a1 0.10 __ 0.25 a2 __ 1.45 __ b 0.33 0.41 0.51 c 0.19 0.20 0.25 d 9.80 9.91 10.01 e 5.79 5.99 6.20 e1 3.81 3.91 3.99 e __ 1.27 __ l 0.38 0.71 1.27 __ __ 0.08 0 __ 8 1.all dimensions are in millimeters. 2.dimension does not include mold protrusions. part markin g information & packin g : sop-16 y advanced power electronics corp. symbols u3048m ywwsss package code part number date code (ywwsss) y last digit of the year ww week sss sequence 16
package outline : tssop-16 millimeters symbols min nom max a 1.05 1.10 1.20 a1 0.05 0.10 0.15 a2 __ 1.00 1.05 b 0.20 0.25 0.28 c __ 0.13 __ d 4.90 5.08 5.10 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e __ 0.65 __ l 0.50 0.60 0.70 __ __ 0.08 0 4 8 part marking information & packing : tssop-16 y advanced power electronics corp. u3048o ywwsss package code part number date code (ywwsss) y last digit of the year ww week sss sequence 17

▲Up To Search▲

Price & Availability of ADVANCEDPOWERELECTRONICSCORP-APU3048O

	To Download ADVANCEDPOWERELECTRONICSCORP-APU3048O Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .